Understanding Gated Dlatches: One-Bit Memory Devices Explained

A gated dlatch is a one-bit memory device. The D stands for data. A gated Dlatch is also referred to as a data

latch or simply a Dlatch. We're going to look at how a Dlatch can be built from a gated SR latch and examine its behavior

with a timing diagram. Let's first remind ourselves of a potential problem associated with gated

SR latches. Remember a gated SR latch can be constructed from NAND gates. A gated SR latch is an active high latch.

In other words, both S and R are normally at low voltage representing zeros. And a pulse is required at one of

these in order to set or reset the latch. Meanwhile, if the output at Q is high,

the latch is set and it's storing a one. But if Q is low, the latch is not set and it's storing a zero.

The gated SR latch has a third input E which when high enables the latch. The latch is said to be transparent when

it's enabled. As elegant as it is, we have a potential problem with this circuit.

There's a possibility that S and R could be made high simultaneously. This would be like asking the latch to

store a one and a zero at the same time, which is nonsense. In reality, both Q and not Q would become high. Then, if

both S and R fell to zero at the same time, we'd have a race condition. The cross-connected NAND gates would race

each other to feed back their outputs, making it impossible to predict the next state of the latch.

This would be like tossing a coin. the latch would end up in either one of its two stable states. Needless to say, this

kind of unpredictability in an electronic circuit is usually unacceptable.

So, what can we do about it? By simply inverting input S with a notgate, then feeding this notgate's

output into R so that R and S are always the opposite of each other, the forbidden input combination of S= 1 and

R= 1 can never be applied. Now we can rename input S to D. D for data. And now we have a oneinput gated

SR latch, otherwise known as a Dlatch. Let's see it in action. While E is high, if D is high, then so

is Q. While E is high, if D changes to low, then so does Q.

You can see that while E is high, Q is always the same as D. And because we're using a notgate like this, there's no

possibility of the Dlatch ever ending up in a forbidden state like an SR latch might.

This is still a latch, of course, because if E falls to zero, output Q will retain its previous value. And the

Dlatch will no longer respond to changes in D. It's locked in its current state. Let's return to our gated SR latch for a

moment. By cleverly rewiring the same four NAND gates like this, we've built a Dlatch in

a different way. It does exactly the same thing as the Dlatch that we built by using a notgate. But because we're

using less components, this version is more efficient and cheaper to make. Let's look at both designs together.

We can see that this new version is taking advantage of the fact that the output of the top NAND gate is always

the inverse of D as long as the latch is enabled. So this output is fed back into the lower gate. A rather elegant

solution. Let's quickly check it is indeed doing the same thing by tracing the highs and

lows through the gates again. At the moment E is high, D is high and so is Q. E is still high. D goes low. And so does

Q. E goes low. D and Q remain as they were low. E is still low. D becomes high. But Q

remains low. E becomes high again. D is already high. So Q goes high.

Now let's examine the behavior of a Dlatch on a timing diagram. This type of analysis might reveal some behavior we

haven't spotted yet. First though, we're going to give the Dlatch its own symbol so we can focus on what it does rather

than how it was built. We're interested in the relationship between D, E, and Q. So here they are on

a shared time axis. Not Q is always the inverse of Q. So we haven't included it on this diagram.

At our starting point, E is high. In other words, the Dlatch is enabled. D is low and therefore so is Q.

When D goes high, so does Q. When D goes low, so does Q. You can see that while E is high, Q is following D.

When E goes low, Q is latched. It can't change. So we can see here changes in D are not being

reflected in Q. D at the moment is low. Q is high. But when E goes high again, Q reflects D.

And once again Q is following D. On this diagram, we see E going low again. So Q is no longer following D

until of course E goes high again. To summarize then, a Dlatch, otherwise known as a data latch, can be built from

a gated SR latch, either by including a notgate or by simply rewiring the existing NAND gates.

Regardless of how it was built, the Dlatch has its own symbol and its behavior can be described on the timing

diagram. The essence of this behavior is that the output follows the input while the Dlatch is enabled. If the Dlatch is

disabled, it retains its current state. This means the Dlatch can be used to capture and store one bit of data. It's

a one bit memory device. Dlatches are useful for converting parallel data into serial data. A group

of Dlatches can hang on to several bits of data while a multipplexer accesses them one at a time and places them onto

a serial transmission line. Typically, Dlatches are found in input output ports.

One final point, latches are sometimes referred to as flip-flops, but strictly speaking this is not correct. Latch

circuitry does however form the basis of a flip-flop, and I'll be looking at these later.