Complete Timestamps: How Standard Cells Are Placed Inside a Chip | Physical Design Guide
[0:00] Introduction to Placement This section introduces the placement stage of VLSI physical design, explaining how logical cells from the netlist are assigned physical locations on the floor plan, with SRAM macros fixed and standard cell rows prepared. [0:30] Connectivity and Hierarchy The importance of connectivity graphs and hierarchical instance paths is discussed, showing how related logic (e.g., memory interface) is placed near fixed macros based on net connections rather than names alone. [1:30] Why Placement Matters for Timing Two placement solutions are compared to illustrate how cell proximity affects signal delay, setup slack, and overall chip performance, emphasizing the trade-offs in wire length and path optimization. [2:30] Inputs for Placement The required inputs for placement are listed, including the gate-level netlist, physical library, timing libraries, floor plan, constraints, and RC technology data, along with checks for database integrity. [4:00] Global Placement and Legalization Global placement uses algorithms like min-cut or quadratic methods to estimate cell positions, followed by legalization to align cells to row grids and remove overlaps, with detailed placement refining the solution. [5:30] Timing-Driven Optimization Placement optimization focuses on timing-critical paths, using weights and cell resizing to improve slack, while balancing area and power costs, and iterating with legalization and timing updates. [7:00] Congestion and Density Trade-offs The section explains how local cell density and routing congestion are managed, noting that minimizing wire length alone is insufficient; a good placer spreads cells and protects macro interfaces for routability. [8:30] Advanced Node Considerations At advanced nodes (e.g., 7nm/5nm), PVT corners, temperature inversion, and variation methods (LVF, POCV) affect timing, with net delays estimated from cell positions and interconnect data across multiple corners. [10:00] Evaluating Placement Results Placement reports are analyzed using fictional data, showing improvements in WNS, TNS, and violations after optimization, with emphasis on consistent scenarios and the need to inspect physical displays and logs. [12:00] Conclusion and Next Steps The placement checkpoint is summarized as a handoff to clock tree synthesis, with a preview of future topics (CTS, routing, STA) and a practical tool (placement_qor.py) for analyzing placement quality.
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