Introduction to Snooping Based Cache Coherence Protocol
In this session, we delve into the snooping based cache coherence protocol and its mechanisms for ensuring data consistency across caches in multiprocessor systems.
Recap of Cache States and Coherence Protocols
- Cache lines store coherence information managed by cache controllers.
- Two primary protocols: snooping-based and directory-based cache coherence.
How Snooping Based Protocol Works
- A shared variable (e.g., 'a' initialized to 7 in main memory) is accessed by processors.
- When a processor (e.g., P1) attempts to access 'a' but lacks it in cache, it results in a compulsory miss.
- P1 broadcasts a read request on the shared bus, observed by all caches (which are constantly snooping).
- If no cache contains 'a', main memory supplies the data.
- The cache line now holds 'a' with its state set to 'shared'.
Handling Multiple Reads
- When another processor (e.g., P3) requests 'a', caches without 'a' ignore the request.
- Caches with 'a' in 'shared' state also do not supply but allow main memory to respond.
- The requesting cache (P3) loads 'a' and marks the cache line as 'shared'.
Write Operations and State Transitions
- When P1 increments 'a', the cache line state changes from 'shared' to 'modified'.
Write Invalidate Strategy
- P1 issues an invalidation signal on the bus.
- Other caches (e.g., P3) invalidate their copies, setting their state to 'invalid'.
- Updates to main memory occur immediately in write-through or during cache replacement in write-back strategies.
Write Update Strategy
- Instead of invalidating, P1 broadcasts the updated value to all caches.
- All caches update their copies and mark their cache line states as 'shared'.
Coherence Miss Explained
- If a processor (P3) tries to modify 'a' but its cache line is 'invalid', it experiences a coherence miss.
- The processor must fetch the updated value from the bus or memory before proceeding.
Practical Relevance
- Modern multiprocessors from AMD and Intel implement variations of snooping-based protocols to manage cache coherence effectively.
- For a deeper understanding of how these concepts fit into the broader landscape of computing, refer to the Comprehensive Guide to Computer Architecture and RISC-V Overview.
Conclusion
- Snooping based cache coherence protocols maintain data uniformity by broadcasting cache transactions across a shared bus and managing cache line states.
- It allows processors to coordinate cache contents efficiently, supporting both write invalidate and write update strategies.
In the next session, we will explore the directory-based cache coherence protocol, contrasting its approach with snooping methods.
hello everyone and welcome back in this session we are going to talk about the snooping based cache coherency protocol
in details so without any further ado let's get to learning now during our previous session we
learnt about the various states which can be specified with respect to the cache a line now these are the coherence
informations which are to be stored in the respective cache controllers thereafter we came across the different
cache coherency protocols that is the snooping and directory based protocol in this session we are going to observe and
try to understand the working principle of the snooping based cache equivalence protocol
now let's try and understand the snooping based protocol with the help of this illustration let me demonstrate how
the coherency is maintained here throughout similar to our example that we used in
order to explain the cache coherence problem here we also have the same variable a
initialized to 7 residing inside the main memory at this point of time suppose p1 wants
to access a since p1 doesn't have it in its cache a it will be a compulsory miss so p1 will
generate a read request for a and place it on the shared bus now this request is a broadcast request
that means all the other caches will be able to read and understand it because their cache controllers are snooping on
the shared bus at all times since none of the caches have the variable a in them therefore they will
simply ignore the request and finally a will be provided by the main memory itself through the shared bus to the p1
cache now once p1 has it in its cache controller the coherence information for that particular line which has a the
state will be specified as shared similarly suppose p3 also wants to access a and now a read request for a
will be placed on the bus by p3 at this point p2 and p4 since they don't have any copy of a will simply ignore
the request however p1 has a copy of a present in its cache but then again it's in shared state
so instead of providing a to p3 it will ignore the request therefore just to maintain the uniform nature of the
protocol finally a will be provided to p3 by the main memory now once p3 acquires a it will also
store the coherence information in its controller for the cache line containing a as shared
now imagine at this instance p1 performs the operation on a that is it increments the value of a by one
for this the state of the line having a will be promoted from shared to modified now if we are using write invalidate
variation of snooping based protocol the moment p1 updates the value of a p1 will place an invalidation signal on the bus
ordering all the the caches to invalidate their local copies of a reading this the cache controller of p3
will demote the state of cache a line having a from shared to invalid now if we implement write
invalidate right through this particular modification done by p1 will be propagated to the main memory
right away updating the value of a as eight and in case we are using right back
strategy the modification will be propagated to the main memory during the next cache replacement
now let me introduce a very interesting situation to you suppose at this point p3 wants to
perform its operation on a that is it wants to decrement the value of a by one now if you observe closely p3 does have
a in its own cache a but it's in invalid state so p3 can't really use the value that it
has inside its cache and this situation will be considered as another miss now if you remember when we came across
various types of cache misses we learned the term coherence miss and we were supposed to learn about this
during the discussion of cache coherence guess what this is the session where we have just seen that that means this
particular mess is nothing but the coherence mess now let's talk about the right update
strategy in write update instead of generating an invalidation request p1 as soon as it updates a will generate an
update request and place it on the shared bus commanding all the other caches to update their local copies of a
and once all the copies of a are updated all the different cache controller will specify the states as shared
now in write update for right through and right back similar kind of strategy will be followed as we did in case of
write invalidate fun fact the amd and intel multiprocessors use variations of
snooping based protocol for maintaining cache coherence so this is how snooping based cache
coherence protocol works all right people that will be all for this session i hope now you have a clear
understanding of snooping based protocol in the next session we are going to look into the directory based protocol so i
hope to see you in the next one thank you all for watching [Music]
[Applause] [Music]
A snooping based cache coherence protocol is a method used in multiprocessor systems to maintain consistent data across multiple caches. It works by having caches monitor, or 'snoop,' a shared communication bus to detect and respond to operations that could affect cached data, ensuring that all processors have a coherent view of memory. This is crucial for system correctness and efficient parallel processing.
During a read, if a processor's cache lacks the data, it broadcasts a read request; caches respond by either supplying data or allowing memory to do so, marking the cache line as 'shared'. For write operations, the cache line changes from 'shared' to 'modified' state. The writing processor either invalidates other copies ('write invalidate') or updates them with new data ('write update'), ensuring consistency across caches.
In the write invalidate strategy, when a processor writes to a cache line, it sends an invalidation signal causing all other caches holding that line to mark it invalid, preventing stale reads. In contrast, the write update strategy broadcasts the new data to all caches holding that line, allowing them to update their copies and keep the line in a 'shared' state. Both aim to maintain data coherence but differ in communication and update approaches.
A coherence miss occurs when a processor attempts to write to a cache line marked as 'invalid' in its cache. Since the cache does not have the latest data, the processor must fetch the updated value from either the shared bus or memory before proceeding with the write. This ensures the processor works on the most recent data, maintaining coherence across caches.
Modern processors from AMD and Intel use advanced variations of snooping based cache coherence protocols that efficiently monitor and manage cache states across many processor cores. These implementations use optimized bus architectures and state tracking to coordinate cache contents, often integrating both write invalidate and write update mechanisms to balance performance and consistency.
Snooping protocols rely on broadcasting cache transactions on a shared bus that all caches monitor actively, making them well-suited for smaller-scale systems with simpler interconnects. In contrast, directory-based protocols use a centralized directory to track which caches store copies of data, reducing bus traffic and scaling better for larger multiprocessor systems. The video focuses on snooping; the next session covers directory-based protocols.
For a comprehensive understanding of computer architecture and how cache coherence fits within it, you can refer to the "Comprehensive Guide to Computer Architecture and RISC-V Overview" available at https://lunanotes.io/summary/comprehensive-guide-to-computer-architecture-and-risc-v-overview. This resource provides in-depth coverage of these topics and their practical applications.
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